The present invention relates to a high-speed semiconductor memory device, and more particularly to an apparatus and method for stably initializing an error detection code (EDC) pin during an initial operation of the high-speed semiconductor memory device.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by the addresses.
As the operating speed of the system increases and semiconductor integrated circuit technologies are advanced, semiconductor memory devices are required to input and output data at higher speed. In order for faster and more stable operation of semiconductor memory devices, a variety of circuits inside the semiconductor memory devices must be able to operate at a high speed and transfer signals or data between the circuits at a high speed.
A fast operation of the semiconductor memory device can be achieved by executing a plurality of internal operations at higher speed and increasing signal and data input/output speeds. As one example, a double data rate (DDR) synchronous dynamic random access memory (DRAM) can achieve a high-speed data transfer by transferring data in synchronization with falling and rising edges of a system clock. Since the DDR SDRAM can input or output two data through one input/output terminal in one cycle of the system clock, its data input/output speed is higher than that of a typical semiconductor memory device. At present, a new semiconductor memory device has been proposed which can input and output four data in one cycle of a system clock.
The DDR SDRAM adopts a prefetch operation in order to output data at a high speed. The prefetch operation refers to an operation to previously store data or commands in a high-speed storage before the data or commands are processed. For example, the DDR SDRAM accesses memory cells and outputs 2-bit data through a data pad in each clock cycle. Such a prefetch operation is referred to as a 2-bit prefetch operation. In addition, a DDR2 SDRAM adopts a 4-bit prefetch operation to access memory cells and output 4-bit data to a data pad in each clock cycle. A DDR3 SDRAM adopts an 8-bit prefetch operation to access memory cells and output 8-bit data to a data pad in each clock cycle.
In this way, the data input/output speed must have been increased in order to enable the semiconductor memory device to operate at a high speed in synchronization with a high-frequency clock. Hence, the semiconductor memory device adopts an operation scheme that reads or writes data corresponding to a minimum burst length to each data input/output pad (DQ) in response to one-time read or write command. This scheme is referred to as an N-bit prefetch operation, where N is equal to the minimum burst length.
As described above, since a semiconductor memory device recently proposed is required to input or output four data in one cycle of a system clock, it adopts an 8-bit prefetch operation for high-speed data input/output. Eight data output from unit cells in response to one read command are transferred in parallel through the corresponding sense amplifiers and data input/output lines. The parallel data are serialized in order to output them through one data pad. In order to control such an operation, the semiconductor memory device includes a plurality of data output circuits respectively connected to a plurality of data input/output pads.
If not a physical damage inside a system, a data transfer error is generated by the mismatching of operation timing between a data transmitting side and a data receiving side. In general, since an operation margin is sufficient when a semiconductor memory device and a data processor transfer data in synchronization with a low-frequency system clock, data reliability is not greatly doubtful. However, if a semiconductor memory device and a data processor operate in synchronization with a clock system having a high frequency of, for example, 4 Gbps, data reliability may be greatly degraded because the operation margin for data transfer is not sufficient. Also, while the operating speed of the semiconductor memory device is increasing and four data are input/output in one cycle of the system clock, a separate apparatus and method are additionally required for ensuring the reliability as to whether the data transfer is exactly achieved. As one approach, a semiconductor memory device recently proposed includes a pin through which an error detection code (EDC) is output. The output of the EDC aims at detecting the error of data transferred in the read or write operation.
In order to ensure the reliability of data transfer, the semiconductor memory device outputs a cyclic redundancy check (CRC) data through an EDC pin. When the semiconductor memory device outputs the CRC data, the data processor receives the CRC data and detects the data error.